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pseudo differential input, 1 msps 10- and 12-bit adcs in an 8-lead sot-23 ad7441/ad7451 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features fast throughput rate: 1 msps specified for v dd of 2.7 v to 5.25 v low power at max throughput rate: 4 mw max at 1 msps with v dd = 3 v 9.25 mw max at 1 msps with v dd = 5 v pseudo differential analog input wide input bandwidth: 70 db sinad at 100 khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface: spi?/qspi?/microwire?/dsp compatible power-down mode: 1 a max 8-lead sot-23 and msop packages applications transducer interface battery-powered systems data acquisition systems portable instrumentation functional block diagram 03153-a-001 v ref t/h control logic 12-bit successive approximation adc gnd sclk sdata cs v dd ad7441/ad7451 v in+ v in? figure 1. general description the ad7441/ad7451 1 are, respectively, 10-bit and 12-bit high speed, low power, successive approximation (sar) analog-to- digital converters that feature a pseudo differential analog input. these parts operate from a single 2.7 v to 5.25 v power supply and achieve very low power dissipation at high throughput rates up to 1 msps. the ad7441/ad7451 contain a low noise, wide bandwidth, differential track-and-hold amplifier (t/h) that handles input frequencies up to 3.5 mhz. the reference voltage for these devices is applied externally to the v ref pin and can range from 100 mv to v dd , depending on the power supply and what suits the application. the conversion process and data acquisition are controlled using cs and the serial clock, allowing the device to interface with microprocessors or dsps. the input signals are sampled on the falling edge of cs when the conversion is also initiated. the sar architecture of these parts ensures that there are no pipeline delays. 1 protected by u.s. patent number 6,681,332 product highlights 1. operation with 2.7 v to 5.25 v power supplies. 2. high throughput with low power consumption. with a 3 v supply, the ad7441/ad7451 offer 4 mw max power consumption for a 1 msps throughput rate. 3. pseudo differential analog input. 4. flexible power/serial clock speed management. the conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. these parts also feature a shutdown mode to maximize power efficiency at lower throughput rates. 5. variable voltage reference input. 6. no pipeline delay. 7. accurate control of the sampling instant via a cs input and once-off conversion control. 8. enob > 10 bits typically with 500 mv reference.
ad7441/ad7451 rev. a | page 2 of 24 table of contents ad7451 specifications..................................................................... 3 ad7441 specifications..................................................................... 5 timing specifications....................................................................... 7 absolute maximum ratings............................................................ 8 esd caution.................................................................................. 8 pin configurations and function descriptions ........................... 9 terminology .................................................................................... 10 typical performance characteristics ........................................... 11 circuit information ........................................................................ 13 converter operation.................................................................. 13 adc transfer function............................................................. 13 typical connection diagram ................................................... 14 analog input ............................................................................... 14 digital inputs .............................................................................. 15 reference ..................................................................................... 15 serial interface ............................................................................ 16 modes of operation ....................................................................... 18 normal mode.............................................................................. 18 power-down mode .................................................................... 18 power vs. throughput rate....................................................... 20 microprocessor and dsp interfacing ...................................... 20 grounding and layout hints..................................................... 22 evaluating performance ............................................................ 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 24 revision history 2/04data sheet changed from rev. 0 to rev. a updated format ..................................................................... universal changes to general description ....................................................... 1 changes to table 1 footnotes ............................................................. 4 changes to table 2 footnotes ............................................................. 6 changes to table 3 footnotes ............................................................. 7 changes to table 5 .............................................................................. 9 updated figures 7, 8, and 9 .............................................................. 13 changes to figure 23......................................................................... 16 changes to reference section .......................................................... 17
ad7441/ad7451 rev. a | page 3 of 24 ad7451 specifications table 1. v dd = 2.7 v to 5.25 v; f sclk = 18 mhz; f s = 1 msps; v ref = 2.5 v; t a = t min to t max , unless otherwise noted. temperature ranges for a, b versions ?40c to +85c. parameter test conditions/comments a version b version unit dynamic performance f in = 100 khz signal-to-noise ratio (snr) 1 v dd = 2.7 v to 5.25 v 70 70 db min signal to (noise + distortion) (sinad) 1 v dd = 2.7 v to 3.6 v 69 69 db min v dd = 4.75 v to 5.25 v 70 70 db min total harmonic distortion (thd) 1 v dd = 2.7 v to 3.6 v; ?78 db typ ?73 ?73 db max v dd = 4.75 v to 5.25 v; ?80 db typ ?75 ?75 db max peak harmonic or spurious noise 1 v dd = 2.7 v to 3.6 v; ?80 db typ ?73 ?73 db max v dd = 4.75 v to 5.25 v; ?82 db typ ?75 ?75 db max intermodulation distortion (imd) 1 fa = 90 khz; fb = 110 khz second-order terms ?80 ?80 db typ third-order terms ?80 ?80 db typ aperture delay 1 5 5 ns typ aperture jitter 1 50 50 ps typ full-power bandwidth 1 , 2 @ ?3 db 20 20 mhz typ @ ?0.1 db 2.5 2.5 mhz typ dc accuracy resolution 12 12 bits integral nonlinearity (inl) 1 1.5 1 lsb max differential nonlinearity (dnl) 1 guaranteed no missed codes to 12 bits 0.95 0.95 lsb max offset error 1 3.5 3.5 lsb max gain error 1 3 3 lsb max analog input full-scale input span v in+ ? v inC v ref v ref v absolute input voltage v in+ v ref v ref v v inC 3 v dd = 2.7 v to 3.6 v ?0.1 to +0.4 ?0.1 to +0.4 v v dd = 4.75 v to 5.25 v ?0.1 to +1.5 ?0.1 to +1.5 v dc leakage current 1 1 a max input capacitance when in trac k/hold 30/10 30/10 pf typ reference input v ref input voltage 1% tolerance for specified performance 2.5 4 2.5 4 v dc leakage current 1 1 a max v ref input capacitance when in tr ack/hold 10/30 10/30 pf typ logic inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current, i in typically 10 na, v in = 0 v or v dd 1 1 a max input capacitance, c in 5 10 10 pf max logic outputs output high voltage, v oh v dd = 4.75 v to 5.25 v; i source = 200 a 2.8 2.8 v min v dd = 2.7 v to 3.6 v; i source = 200 a 2.4 2.4 v min output low voltage, v ol i sink = 200 a 0.4 0.4 v max floating-state leakage current 1 1 a max floating-state output capacitance 5 10 10 pf max output coding straight (natural) binary straight (natural) binary
ad7441/ad7451 rev. a | page 4 of 24 parameter test conditions/comments a version b version unit conversion rate conversion time 888 ns with an 18 mhz sclk 16 16 sclk cycles track-and-hold acquisition time 1 sine wave input 250 250 ns max full-scale step input 290 290 ns max throughput rate 1 1 msps max power requirements v dd 2.7/5.25 2.7/5.25 v min/max i dd 6 , 7 normal mode (static) sclk on or off 0.5 0.5 ma typ normal mode (operational) v dd = 4.75 v to 5.25 v 1.95 1.95 ma max v dd = 2.7 v to 3.6 v 1.45 1.45 ma max full power-down mode sclk on or off 1 1 a max power dissipation normal mode (operational) v dd = 5 v; 1.55 mw typ for 100 ksps 6 9.25 9.25 mw max v dd = 3 v; 0.6 mw typ for 100 ksps 6 4 4 mw max full power-down v dd = 5 v; sclk on or off 5 5 w max v dd = 3 v; sclk on or off 3 3 w max 1 see section. terminology 2 analog inputs with slew rates exceeding 27 v/s (full-scale input sine wave > 3.5 mhz) within the acquisition time could cause the converter to return an incorrect result. 3 a small dc input is applied to v inC to provide a pseudo ground for v in+ . 4 the ad7451 is functional with a refere nce input in the range 100 mv to v dd . 5 guaranteed by characterization. 6 see the power vs. throughput section. 7 measured with a full-scale dc input.
ad7441/ad7451 rev. a | page 5 of 24 parameter test conditions/comments b version unit ad7441 specifications table 2. v dd = 2.7 v to 5.25 v; f sclk = 18 mhz; f s = 1 msps; v ref = 2.5 v; t a = t min to t max , unless otherwise noted. temperature ranges for b version ? 40c to +85c. dynamic performance f in = 100 khz signal to (noise + distortion) (sinad) 1 61 db min total harmonic distortion (thd) 1 2.7 v to 3.6 v; ?77 db typ ?72 db max 4.75 v to 5.25 v; ?79 db typ ?73 db max peak harmonic or spurious noise 1 2.7 v to 3.6 v; ?80 db typ ?72 db max 4.75 v to 5.25 v; ?82 db typ ?74 db max intermodulation distortion (imd) 1 fa = 90 khz, fb = 110 khz second-order terms ?80 db typ third-order terms ?80 db typ aperture delay 1 5 ns typ aperture jitter 1 50 ps typ full-power bandwidth 1 , 2 @ ?3 db 20 mhz typ @ ?0.1 db 2.5 mhz typ dc accuracy resolution 10 bits integral nonlinearity (inl) 1 0.5 lsb max differential nonlinearity (dnl) 1 guaranteed no missed codes to 10 bits 0.5 lsb max offset error 1 1 lsb max gain error 1 1 lsb max analog input full-scale input span v in+ ? v inC v ref v absolute input voltage v in+ v ref v v inC 3 v dd = 2.7 v to 3.6 v ?0.1 to +0.4 v v dd = 4.75 v to 5.25 v ?0.1 to +1.5 v dc leakage current 1 a max input capacitance when in track/hold 30/10 pf typ reference input vref input voltage 1% tolerance for specified performance 2.5 4 v dc leakage current 1 a max vref input capacitance when in track/hold 10/30 pf typ logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i in typically 10 na, v in = 0 v or v dd 1 a max input capacitance, c in 5 10 pf max logic outputs output high voltage, v oh v dd = 4.75 v to 5.25 v ; i source = 200 a 2.8 v min v dd = 2.7 v to 3.6 v; i source = 200 a 2.4 v min output low voltage, v ol i sink = 200 a 0.4 v max floating-state leakage current 1 a max floating-state output capacitance 5 10 pf max output coding straig ht (natural) binary
ad7441/ad7451 rev. a | page 6 of 24 parameter test conditions/comments b version unit conversion rate conversion time 888 ns with an 18 mhz sclk 16 sclk cycles track-and-hold acquisition time 1 sine wave input 250 ns max step input 290 ns max throughput rate 1 msps max power requirements v dd 2.7/5.25 v min/max i dd 6 , 7 normal mode (static) sclk on or off 0.5 ma typ normal mode (operational) v dd = 4.75 v to 5.25 v 1.95 ma max v dd = 2.7 v to 3.6 v 1.25 ma max full power-down mode sclk on or off 1 a max power dissipation normal mode (operational) v dd = 5 v; 1.55 mw typ for 100 ksps 6 9.25 mw max v dd = 3 v; 0.6 mw typ for 100 ksps 6 4 mw max full power-down v dd = 5 v; sclk on or off 5 w max v dd = 3 v; sclk on or off 3 w max 1 see the terminology section. 2 analog inputs with slew rates exceeding 27 v/s (full-scale input sine wave > 3.5 mhz) within the acquisition time may cause t he converter to return an incorrect result. 3 a small dc input is applied to v inC to provide a pseudo ground for v in+ . 4 the ad7441 is functional with a refere nce input in the range 100 mv to v dd . 5 guaranteed by characterization. 6 see the power vs. throughput section. 7 measured with a full-scale dc input.
ad7441/ad7451 r e v. a | pa ge 7 o f 2 4 parameter limit at t min , t ma x unit description timing specifications g u a r an t e ed b y c h a r ac t e r i za tio n . al l in p u t sig n a l s a r e s p ecif ied wi t h tr = tf = 5 n s (10% t o 90% o f v dd ) and t i me d f r om a vol t age l e vel of 1.6 v . s e e f i gur e 2, f i gur e 3, a n d th e s e r i al i n t e r f ace s e c t ion. table 3. v dd = 2.7 v to 5.2 5 v; f scl k = 18 mh z ; f s = 1 msps; v re f = 2. 5 v; t a = t min to t max , un less otherwi s e n o ted. f sclk 1 10 khz min 18 mhz max t con v ert 16 t sclk t sclk = 1/f sclk 888 ns max t qu iet 60 ns min minimum quiet time between the end of a se rial read and the next falling edge of cs t 1 10 ns min minimum cs pulse wid t h t 2 10 ns min cs falling edge to sclk falling edge set-up time t 3 2 20 ns max delay from cs falling edge until s d ata three-state disabled t 4 40 ns max data access time after sclk falling edge t 5 0.4 t sclk ns min sclk high pulse width t 6 0.4 t sclk ns min sclk low pul s e wid t h t 7 10 ns min sclk edge to da ta valid hold time t 8 3 10 ns min sclk falling edge to sdata three-state enabled 35 ns max sclk falling edge to sdata three-state enabled t power - up 4 1 s max power-up time from full power-down 1 mark/ s pace ratio for the sc lk input is 40/60 to 60/40. 2 mea s ure d with the loa d circuit o f a n d d e f i ne d as the time re quire d fo r the o u tput to cro s s 0.8 v or 2.4 v wi th v figu re 4 f i g ure 4. dd = 5 v and the time re quired f o r an o u tput to cross 0.4 v or 2.0 v for v dd = 3 v . 3 t 8 i s d e ri ved f r om t h e m e a s ur ed t i m e t a ken by t h e da t a o u t p ut s t o ch a n ge 0. 5 v wh en loa d ed wi t h t h e ci rcui t o f th e m e a s ured numbe r i s the n extrapo l ate d back to re mo ve the e f f e cts of charging o r d i s c harging the 25 pf capacito r. this me ans that the ti me , t 8 , quoted in the timing characteri s t ics , is the true bus rel i nquis h time of the part and is in d e pe nde nt o f the bus lo ad ing. 4 se e s e ct i o n . powe r- up ti m e t 3 t 2 t 4 t 7 t 8 t 6 t 1 t 5 t quiet t convert cs sclk s dat a 4 leading zeros three-state 12 3 4 5 1 3 1 4 1 5 1 6 0 0 0 0 db11 db10 db2 db1 db0 b 03153-a - 002 f i g u re 2. a d 74 51 s e ri al int e r f ace ti mi ng d i ag r a m t 3 t 2 t 4 t 7 t 8 t 6 t 1 t 5 t quiet t convert cs sclk sdata 4 leading zeros 2 trailing zeros three-state 12 3 4 5 1 3 1 4 1 5 1 6 0 0 0 0 db9 db8 db0 0 0 b 03153-a - 003 f i g u re 3. a d 74 41 s e ri al int e r f ace ti mi ng d i ag r a m
ad7441/ad7451 r e v. a | pa ge 8 o f 2 4 p a r a m e t e r r a t i n g absolute maximum ratings s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . table 4.t a = 25 c, unl e s s ot herwi s e not e d. v dd to gnd ?0.3 v to +7 v v in+ to gnd ?0.3 v to v dd + 0.3 v v inC to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to +7 v digital output v o ltage to gnd ?0.3 v to v dd + 0.3 v v ref to gnd ?0.3 v to v dd + 0.3 v input current to any pin ex cept supplies 2 10 ma operating tem p erature range commercia l (a, b version) ?40c to +85c storage temperature range ?65c to +150c junction tempe r ature 150c ja thermal impedance 205.9c/w (ms op) 211.5c/w (sot-23) jc thermal impedance 43.74c/w (ms op) 91.99c/w (sot-23) lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c e s d 1 k v 2 transient currents of up to 100 ma do not cause s c r latch-up. 03153-a - 004 1.6ma i ol 200 ai oh 1.6v to output pin c l 25pf f i gure 4 . l o a d cir c ui t fo r di g i ta l o u tput t i m i ng sp eci f ic ati o ns esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad7441/ad7451 r e v. a | pa ge 9 o f 2 4 pin conf igurations and f u ncti on descriptions 03153-a - 005 v ref v in+ v in? gnd 8 7 6 5 v dd 1 sclk 2 sdata 3 cs 4 ad7441/ ad7451 top view (not to scale) f i g u re 5. 8-l e ad s o t - 23 03153-a - 006 v dd sclk sdata cs 8 7 6 5 v ref 1 v in+ 2 v in? 3 gnd 4 ad7441/ ad7451 top view (not to scale) f i g u re 6. 8-l e ad m s op ta ble 5. pi n f u nct i on d e s c ri pt i o ns mnemonic function v ref reference input for the ad7441 /ad7451. an exte rnal reference i n the range 100 mv to v dd must be applied to this input. the specified refere nce input is 2.5 v. this pin should be decoupled to gnd with a capacitor of at least 0.1 f. v in+ noninverting analog input. v inC inverting input. this pin sets th e ground reference point for the v in+ input. connect to ground or to a dc offset to provide a pseudo ground. gnd analog ground. ground reference point for all circuitry on the a d 7441/ad7451. all analog in put signals and any external reference sign al should be re fer r ed to this gnd voltage. cs chip select. acti ve low logic input. this input pr ovides the dual function of initiating a conver si on on the ad7441/ad7451 and framing the serial data trans f er. sdata serial data. logi c output. the co nversion result from the ad7441/ad7451 is provided on this output as a serial data stream. the bits are clocked out on the f a lling edge of the sclk input. th e data stream of the ad7451 co nsists of four leading zeros followed by the 12 bits of conve r sion data that are provided ms b first; the data stream of th e ad 7441 consists of four leading zeros, fo llo wed by the 10 bits of conversi on d a ta, follo wed by tw o trailing zeros. in both cases, the output codi ng is straight (natural ) binary. sclk serial clock. log i c input. sclk provides th e serial clock for accessing data from the part. t h is cloc k input is als o used as th e clock source for the conversi on proces s. v dd power supply input. v dd is 2.7 v to 5.25 v. this s u pply should be deco upled to gnd with a 0.1 f capacitor and a 10 f tantalum capacitor.
ad7441/ad7451 rev. a | page 10 of 24 terminology si g n a l to ( n oi s e + d i s t or t i on ) r a t i o t h i s i s t h e me a s u r e d r a t i o of s i g n a l to ( n oi s e + d i stor t i on ) a t t h e o u t p ut o f t h e a d c. th e sig n al i s t h e r m s am pli t ude o f t h e f u n- d a m e n t al . n o i s e i s th e s u m o f all n o n f un d a m e n t al si gn als u p t o half th e s a m p ling f r e q uen c y (f s / 2 ), excl udin g dc. the ra t i o is dep e n d en t on t h e n u m b er o f q u a n t i za tion levels in the dig i t- i z a t i o n p r oce s s; th e m o r e lev e ls, th e sm alle r th e q u a n tiz a ti o n noi s e. t h e t h e o r e t i c a l s i g n a l to ( n oi s e + d i stor t i on ) r a t i o f o r an ide a l n - b i t con v er t e r wi t h a si n e wa v e i n p u t is sig n al to ( n oi s e + d i s t or t i o n ) = (6.02 n + 1.76) d b f o r 12-b i t con v er t e rs, this is 74 db; f o r10-b i t con v er t e rs, 62 db . t o t a l ha r m on i c d i s t or t i on ( t h d ) t o t a l h a r m on i c d i stor t i on i s t h e r a t i o of t h e r m s su m of h a r - m o nics t o the f u ndam e n t al . i n th e ad7441 /ad7451, thd is () 1 2 6 2 5 2 4 2 3 2 2 v v v v v v thd + + + + = log 20 db w h er e v 1 i s th e rm s a m p l i t ud e o f th e fun d a m en tal a n d v 2 , v 3 , v 4 , v 5 , an d v 6 ar e t h e r m s am pl i t udes o f t h e s e c o nd t o t h e sixt h ha r m o n ics. p e a k h a rmo n i c o r s p uri o us n o is e p e a k ha r m o n ic (sp u r i o u s n o is e ) is def i n e d as t h e r a t i o o f t h e r m s val u e o f t h e n e xt la rg es t com p on e n t i n t h e ad c o u t p ut sp e c t r u m ( u p to f s /2, excl udin g dc) t o t h e r m s v a l u e o f t h e f u ndam e n t a l . n o r m a l ly , t h e va lue o f t h is sp e c if ica t ion is d e t e rm in ed b y th e l a r g e s t h a rm o n i c i n th e s p ectr u m , b u t f o r ad cs w h er e t h e ha r m o n ic s a r e b u r i e d i n t h e no is e f l o o r , i t is a n o i s e peak. inte r m o d u l at i o n d i s t or t i on w i t h in p u ts co nsis tin g o f sine wa v e s a t tw o f r eq uen c ies, fa a n d fb , a n a c ti v e d e v i ce wi th n o nlin ea ri ti e s cr ea t e s d i s t o r ti o n p r o d uc ts a t s u m a nd dif f er ence f r e q uen c ies o f mfa nfb w h er e m, n = 0, 1, 2, 3, a nd s o o n . i n ter m o d u l a t ion disto r t i o n ter m s a r e th ose in whic h n e i t her m n o r n a r e eq ual t o zer o . f o r exa m p l e , th e s e co n d -o r d er t e r m s in c l ude (fa + fb) a nd (fa ? fb), while th e th i r d - o r d e r t e rm s in c l ud e (2fa + fb), (2fa ? fb), (fa + 2fb) a nd (fa ? 2fb). the ad7441/ad7451 is t e s t e d usin g th e c c if s t anda r d w h er e tw o in p u t f r e q u e n c ies n e a r t h e t o p end o f t h e i n p u t b a n d wi d t h a r e us ed . i n this cas e , t h e s e cond-o r der t e r m s ar e us ual l y dist an c e d i n f r e q uen c y f r o m t h e o r ig ina l sine wa ves w h i l e t h e thir d-o r der t e r m s a r e us ual l y a t a f r eq uen c y c l os e t o th e in p u t f r e q uen c ies. a s a r e su l t , t h e s e c o nd- and t h ir d - o r der ter m s a r e sp e c if ie d s e p a ra t e ly . t h e c a lc u l a t io n o f t h e in t e r m o d u l a t ion dist o r t i o n is a s p e r t h e th d sp e c if ica t ion w h er e i t is t h e ra t i o o f th e rm s s u m o f th e in d i v i d u al di s t o r ti o n p r od uct s t o th e rm s a m pli t ude o f t h e s u m o f t h e f u ndam e n t als expr es s e d i n db . ap e r t u r e d e l a y this is t h e am oun t o f tim e f r o m the leadin g e d g e o f th e s a m p ling c l o c k un til t h e ad c ac t u al l y ta k e s t h e s a m p le . a p e r tu r e j i tt e r this is t h e s a m p le t o s a m p le var i a t ion in t h e ef fe c t i v e p o i n t i n t i me a t w h ich t h e ac t u a l s a m p l e is t a k e n. fu l l - p o w e r b a n d w i d t h t h e full po w e r ba n d w id th o f a n ad c i s th a t in p u t f r eq uen c y a t w h ich t h e a m pl i t ude o f t h e r e con s t r uc t e d f u ndam e n t al is r e d u ced b y 0.1 db o r 3 db f o r a f u l l s c ale in p u t. in t e g r a l no n l i n e a r i t y ( i n l ) this is t h e maxi m u m d e v i a t io n f r o m a st ra ig h t l i ne p a ssin g th r o ugh th e en d p o i n t s o f th e ad c tra n sf e r fun c ti o n . d i f f erenti a l n o n l i n e a r i ty ( d n l ) this is t h e dif f er en ce b e tw e e n t h e m e as ur e d a nd t h e ide a l 1 l s b c h a n g e be tw een a n y tw o a d j a cen t cod e s i n t h e a d c . off s et e r r o r this is t h e de via t io n o f t h e f i rs t co de tra n si tio n (000000 t o 000001) f r o m th e ide a l (i .e ., a g nd + 1 ls b) ga in er r o r this is t h e de via t io n o f t h e l a s t co de tra n s i tio n (111110 t o 111111) f r o m th e ide a l (i .e ., v ref ? 1 ls b), a f ter t h e o f fs et er r o r has b e en ad j u s t e d o u t. t r a c k-a nd-h o l d a c q u i s iti o n t i me t h e tra c k- a n d-h o ld a c q u i s i t i o n ti m e i s th e m i ni m u m tim e r e q u ir e d fo r t h e t r ack-and- h o ld a m plif ier t o r e ma in in t r ack mo d e for i t s output to re a c h a nd s e t t l e to w i t h i n 0 . 5 l s b of t h e ap p l i e d i n p u t s i g n a l . p o w e r su pp l y re j e c t i o n r a t i o ( p sr r ) the p o w e r su p p ly r e j e c t io n r a t i o is def i n e d as t h e r a t i o o f t h e p o w e r in the ad c o u t p u t a t f u l l -s cale f r eq uenc y , f , t o th e p o w e r o f a 100 mv p-p sin e wa v e a p plied t o t h e ad c v dd su p p ly of fr e q u e n c y f s . t h e fr e q u e n c y o f t h i s i n p u t v a r i e s fr o m 1 k h z to 1 m h z . pss r (d b) = 10 log( pf/p f s ) pf is t h e p o w e r a t f r e q ue n c y f in t h e a d c o u t p u t ; pf s is t h e po w e r a t f r eq u e n c y fs in t h e a d c o u t p u t .
ad7441/ad7451 rev. a | page 11 of 24 typical perf orm ance cha r acte ristics d e fa u l t c o ndi t i o n s: t a = 25c, f s = 1 ms ps, f sc l k = 18 mh z, v dd = 2.7 v t o 5.25 v , v ref = 2.5 v , unles s o t h e r w is e n o t e d. 75 55 60 65 70 10 100 1000 03153-a - 007 frequency (khz) s i nad (db) v dd = 5.25v v dd = 4.75v v dd = 3.6v v dd = 2.7v f i g u re 7. sina d v s . a n al og input f r equ e nc y f o r t h e a d 74 5 1 f o r v a ri ous su p p ly v o lt ag es 0 ? 120 ?80 ? 100 ?60 ?40 ?20 0 100 200 300 400 500 600 700 800 900 1000 03153-a - 008 supply ripple frequency (khz) p s rr (db) 100mv p-p sine wave on v dd no decoupling on v dd v dd = 3v v dd = 5v f i g u r e 8 . p s r r v s . s u pp l y ripp le f r e q ue n c y w i t h o u t s u pp ly de c o u p l i n g 03153-a - 009 frequency (khz) s nr (db) 0 100 200 ?100 ?140 500 ?20 0 ?120 ?40 ?60 ?80 8192 point fft f sample = 1msps f in = 100ksps sinad = 71db thd = ? 82db sfdr = ? 83db 300 400 f i g u re 9. a d 74 51 d y nam i c p e r f or ma n c e f o r v dd = 5 v 03153-a - 010 dnl e r ror (ls b ) code 0.4 0 1024 2048 3072 0.2 0 ? 0.2 ? 0.4 ? 1.0 4096 0.6 0.8 1.0 ? 0.6 ? 0.8 f i g u re 10. t y pic a l d n l f o r t h e a d 74 51 f o r v dd = 5 v 03153-a - 011 inl e rror (ls b ) code 0.4 0 1024 2048 3072 0.2 0 ? 0.2 ? 0.4 ? 1.0 4096 0.6 0.8 1.0 ? 0.6 ? 0.8 f i g u re 11. t y pic a l i n l f o r t h e a d 74 51 f o r v dd = 5 v 03153-a - 012 codes 0 2046 2047 2048 2049 2050 2051 27 codes 24 codes 9949 codes 1,000 2,000 3,000 4,000 5,000 6,000 7,000 8,000 9,000 10,000 f i g u re 12. h i s t og r a m of 1 0 ,0 0 0 conver s i ons of a dc input f o r t h e a d 7 4 5 1
ad7441/ad7451 rev. a | page 12 of 24 5 03153-a - 013 change in dnl (ls b ) ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 012 3 4 4.0 v ref (v) positive dnl negative dnl f i gure 1 3 . change in dnl vs . v ref fo r v dd = 5 v 5 03153-a - 014 change in inl (ls b ) ?2 ?1 0 1 2 3 4 0 1 234 5 v ref (v) positive dnl negative dnl f i gure 1 4 . change in inl vs . v ref for v dd = 5 v 03153-a - 015 e ffe ctiv e numbe r of bits 6 7 8 9 10 11 0 12345 12 v ref (v) v dd = 3v v dd = 5v f i g u re 15. e n ob v s . v ref for v dd = 5 v a n d 3v 03153-a - 016 s nr (db) 0 100 200 300 400 500 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 v ref (v) 8192 point fft f sample = 1msps f in = 100ksps sinad = 61.7db thd = ? 81.7db sfdr = ? 82db f i gur e 1 6 . ad74 41 d y nami c p e r f or manc e 03153-a - 017 dnl e rror (ls b ) 0 256 512 768 1024 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 code f i g u re 17. t y pic a l d n l f o r t h e a d 74 41 03153-a - 018 inl e rror (ls b ) 0 256 512 768 1024 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 code f i g u re 18. t y pic a l i n l f o r t h e a d 74 41
ad7441/ad7451 rev. a | page 13 of 24 circuit i n formation the ad7441/ad7451 a r e 10-b i t a nd 12-b i t, fast, lo w p o w e r , sin g le-s u p p l y , s u cces si v e a p p r o x ima t ion a n alog-t o-dig i tal co n v er t e rs (ad c s) w i t h a ps eudo dif f er en t i al analog in p u t. they o p er a t e wi th a sin g le 2.7 v t o 5.25 v p o w e r s u p p l y a nd a r e ca p a b l e o f thr o ug h p u t ra t e s u p t o 1 ms ps when su p p lie d w i t h a n 1 8 m h z s c l k . t h e y re qu i r e an e x te r n a l re f e re nc e to be a p p l i e d t o t h e v ref pi n . the ad7441/ad7451 ha v e a succes s i v e a p p r o x ima t ion (sar) ad c, an o n -chi p dif f er en t i a l t r ack-and- h o ld am plif ier , a nd a s e r i al in t e r f ace , h o us e d in ei t h er a n 8-lead s o t - 23 o r a n msop p a cka g e . the s e r i al clo c k i n p u t acces s es da t a f r o m t h e p a r t a n d p r o v ides t h e clo c k s o ur ce fo r t h e s u cces si v e a p pr o x ima t ion ad c. th e ad7 441/ad7451 f e a t ur e a p o w e r - do wn o p tion f o r r e d u ce d p o w e r co n s um p t io n b e tw e e n con v ersio n s. t h e p o w e r - do wn fe a t ur e is im ple m e n t e d ac r o ss t h e st and a r d s e r i a l in ter f ace, as des c r i b e d in t h e m o des o f o p er a t i o n s e c t ion. converter operation the ad7441/ad7451 a r e s u cc es si v e a p p r o x ima t io n ad cs b a s e d a r o u nd t w o ca p a ci t i ve d a cs. f i gur e 19 a nd f i gur e 20 sh o w si m p lif i e d s c h e m a t i cs o f t h e ad c in t h e a c q u isi t io n an d c o n v e r s i on ph as e, re sp e c t i vely . t h e a d c i s c o m p r i s e d of co n t r o l log i c, a sar , an d tw o c a p a ci t i v e d a cs. i n f i gur e 19 (a cq ui si ti o n p hase), sw 3 i s c l os ed; sw1 and s w 2 a r e in p o si tio n a, th e co m p a r a t o r is he ld in a ba lan c e d con d i t io n, a nd t h e s a m p ling ca p a c i t o r a r ra ys acq u ir e t h e dif f er en t i al sig n al o n t h e in p u t. 03153-a - 019 v in+ v in? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a f i g u re 19. a d c ac quis it i o n p h as e w h en t h e ad c s t a r ts a con v ersio n (f igur e 20), sw3 o p en s an d sw1 and sw2 m o v e t o p o si tion b , c a usin g the co m p a r a t o r t o beco m e un bala n c e d . b o th in p u t s a r e d i sco n n e c t ed o n ce t h e co n v ersio n b e g i n s . th e co n t r o l log i c a n d t h e c h a r g e r e dis t r i - b u t i on d a cs a r e us e d to ad d and sub t r a c t f i xe d am o u n t s o f ch arge f r om t h e s a m p l i ng c a p a c i tor ar r a y s to b r i n g t h e c o m p ar a t or b a c k i n to a b a l a nc e d c o nd i t i o n . whe n t h e co m p a r a t o r is r e b a lan c e d , t h e c o n v ersio n is com p let e . the co n t r o l log i c g e n e ra t e s t h e ad c s ou t p u t co de . the o u t p u t i m p e da n c e s o f th e so ur ce s d r i v in g th e v in+ and t h e v in C pi ns m u s t b e ma t c h e d; o t h e r w is e t h e tw o in p u ts ha ve dif f er en t s e tt l i n g t i me s , re su lt i n g i n e r ror s . 03153-a - 020 v in+ v in? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a f i g u re 20. a d c co nvers i on p h as e adc tra n s f er func ti on the o u t p u t co din g f o r th e ad74 41/ad7451 is s t ra ig h t (na t ural) b i na r y . th e desig n e d co de tra n s i tio n s o c c u r a t succes si v e ls b val u es (1 ls b , 2 ls b , an d s o on). the ls b size o f th e ad7451 is v ref /4096, a nd th e l s b size o f th e ad7441 is v ref /1024. th e ideal tra n sf er c h a r ac t e r i s t ic o f th e ad7441 /ad7451 is s h o w n in f i gur e 21. 03153-a - 021 000...00 0v adc code analog input 111...11 000...01 111...00 011...11 111...10 000...10 1lsb = v ref /4096 (ad7451) 1lsb = v ref /1024 (ad7441) v ref ? 1lsb 1lsb f i gur e 2 1 . ad74 41 /ad7 45 1 idea l t r a n s f e r cha r a c t e r i stic
ad7441/ad7451 rev. a | page 14 of 24 typical connection diagram f i gur e 22 s h o w s a typ i cal co nn e c tio n dia g ram f o r th e de vice . i n t h is s e t u p t h e g n d p i n is co nne c t e d t o t h e a n a l og g r o u n d plane o f t h e sys t e m . th e v ref p i n is conn ec t e d t o the ad780, a 2.5 v de co u p le d r e feren c e s o ur ce. t h e sig n a l s o ur ce i s co nne c t e d to th e v in + a n a l og in p u t v i a a un i t y ga in b u f f er . a dc v o l t a g e is co nne c t e d to t h e v inC p i n t o p r o v ide a ps eudo g r o u n d fo r t h e v in+ in p u t . th e v dd p i n sh o u l d b e d e co u p le d to a g nd w i t h a 10 f ta n t al u m ca p a c i t o r in p a r a l l e l wi th a 0.1 f cera mic c a p a c i tor . t h e re f e re nc e pi n s h ou l d b e d e c o up l e d to a g n d wi t h a ca p a c i t o r o f a t le ast 0.1 f . th e con v ersio n r e su l t is o u t p ut in a 16- b i t w o r d w i t h 4 l e adin g zer o s fol l o w e d b y t h e ms b o f th e 12-b i t o r 10-b i t r e su l t . th e 10-b i t r e s u l t o f th e ad7441 is f o l l o w ed b y 2 tra i ling zer o s. 03153-a - 022 ad7441/ ad7451 0.1 f 0.1 f 10 f v ref v dd dc input voltage v in+ sclk 2.7v to 5.25v supply serial interface c/ p sdata cs gnd v in ? 2.5v ad780 v ref p-p f i g u re 22. t y pic a l conne c t io n d i ag r a m analog input the ad7441/ad7451 has a ps eudo dif f er en tial a n alog in p u t. the v in+ in pu t i s co u p le d to t h e sig n a l s o ur ce and m u st h a ve an am pl it u d e of v re f p-p t o mak e u s e o f t h e f u l l d y na mic ra n g e o f t h e p a r t . a dc in p u t is a pplie d t o t h e v in C . the v o l t a g e a p plie d t o t h i s i n put prov i d e s an of f s e t f r om g r ou n d or a p s e u d o g r ou nd fo r t h e v in+ i n pu t. p s eudo dif f er en t i al in pu ts s e p a ra t e t h e a n alog i n p u t s i gn al gr o u n d f r o m th e ad c s gr o u n d , all o w i n g d c c o m m on- m o d e vol t age s to b e c a nc el l e d. b e c a u s e t h e a d c op e r a t e s f r om a s i ng l e su p p ly , i t is ne c e ss ar y t o le v e l shif t g r oun d bas e d b i p o l a r sig n als t o co m p l y wi th t h e in p u t r e q u ir emen ts. an o p a m p (f o r exa m p l e , th e ad8021) c a n b e co nf igur e d to r e s c a l e a nd le vel shif t a g r o u nd b a s e d ( b i p o l a r ) si gn al so th a t i t i s co m p a t i b le wi th th e i n p u t ra n g e o f th e ad7441/ad74 51. (s ee f i gur e 23.) w h en a con v ersio n t a k e s pl ace , t h e ps eudo g r o u nd co r r es p o n d s t o 0, a n d t h e maxim u m analog in p u t co r r es p o nds t o 4096 f o r th e ad7451 and 1024 f o r th e ad7441. 03153-a - 023 r 2.5v 1.25v 0v + 1.25v 0v ? 1.25v r 3r 0.1 f r ad7441/ ad7451 v in+ v in+ v in? v ref external v ref (2.5v) f i g u re 23. o p a m p conf ig ur at i o n to l e vel-shif t a bipo la r i n put sig n al analog input structure f i gur e 24 s h o w s th e e q ui valen t cir c ui t o f th e a n alog in p u t s t r u c t ur e o f th e ad7441/ad74 51. th e f o ur dio d es p r o v ide es d p r o t ecti o n f o r th e a n alog i n p u t s . c a r e m u st be ta k e n t o en s u r e t h a t t h e a n alog in p u t sig n als ne v e r exce e d t h e s u p p l y ra ils b y m o r e tha n 300 mv . this ca us es t h es e dio d es t o b e com e fo r w a r d-b i as e d a nd st a r t co nd u c t i n g i n to t h e subst r a t e. t h es e dio d es c a n cond uc t u p to 10 m a w i t h o u t c a usi n g ir r e versi b le da ma g e t o t h e p a r t . th e ca p a c i to rs, c1 in f i gur e 24, a r e typ i cal l y 4 pf a n d can b e a t t r ib ute d p r ima r i l y to p i n c a p a ci t a n c e. the r e sis t o r s a r e l u m p e d com p on e n ts made u p o f th e on r e sis t an c e o f t h e s w i t ch es. the val u e o f t h e s e r e sis t o r s is ty p i cal l y a b o u t 100 ?. th e ca p a ci t o rs, c2, a r e the ad c s s a m p lin g ca p a c i t o rs a nd ha v e a ca p a ci tan c e o f 16 pf typ i cal l y . f o r a c a p pl i c a t i o ns , re mov i ng h i g h f r e q u e nc y c o m p o n e n t s f r o m th e a n alog i n p u t si gnal th r o ugh th e use o f a n r c lo w - pas s f i l t er o n t h e r e le va n t analog in p u t p i n s is r e comm en ded . i n a p plic a t ion s w h er e ha r m o n ic di st o r t i o n and t h e sig n a l -t o- n o is e ra t i o a r e cr i t ica l , t h e a n a l og in pu t sh o u ld b e dr iv en f r o m a lo w im p e d a n c e s o urce . l a rge s o ur ce im p e d a n c es sig n if ican t l y a f fe c t t h e ac p e r f o r ma n c e o f t h e ad c, w h ich ma y n e c e s s i t a t e t h e us e o f a n in pu t b u f f er a m plif ier . the ch o i c e o f t h e am p is a f u n c t i on o f t h e p a r t ic u l ar a p plic a t io n . 03153-a - 024 c1 c2 r1 d d c1 c2 r1 d d v dd v dd v in+ v in? f i g u re 24. equiv a le nt a n al og input c i rcuit ; convers i on p h as e switc h es o p e n ; t r a c k p h ase s w itches c l osed
ad7441/ad7451 rev. a | page 15 of 24 w h en n o am pli f ier is us e d t o dr i v e t h e a n alog in p u t, t h e s o ur ce im p e dan c e sh ou ld be limi t e d to lo w val u es. the maxim u m s o ur ce im p e dance dep e n d s on t h e am o u n t o f tot a l ha r m o n ic d i stor t i on ( t h d ) t h a t c a n b e t o l e r a te d. t h e t h d i n c r e a s e s a s t h e s o ur ce i m p e dan c e i n cr e a s e s a nd p e r f o r ma n c e deg r ades. f i g u re 2 5 show s a g r a p h of t h d ve r s u s an a l o g i n put s i g n a l f r e q uen c y fo r dif f er en t s o ur ce im p e dances. 0 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?1 0 ?2 0 10k 100k 1m 03153-a - 025 input frequency (hz) thd (db) 200 ? 100 ? 62 ? 10 ? t a = 25 c v dd = 5v f i g u re 25. th d v s . a n al og input f r equ e nc y f o r v a ri ous s o ur c e impeda nc es f i g u re 2 6 show s a g r a p h of t h d ve r s u s an a l o g i n put f r e q u e nc y for v a r i ou s su p p ly vol t age s , w h i l e s a m p l i ng a t 1 m s p s w i t h an sclk o f 18 mh z. i n this cas e t h e s o ur ce im p e da n c e is 10 ?. ?50 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 10 100 1000 03153-a - 026 input frequency (khz) thd (dbs ) t a = 25 c v dd = 2.7v v dd = 3.6v v dd = 4.75v v dd = 5.25v f i g u re 26. th d v s . a n al og input f r equ e nc y f o r v a ri ous su p p ly v o lt ag es digi tal in p u ts the dig i tal in p u ts a p p l ie d t o t h e ad7441/ad74 51 a r e n o t limi te d b y t h e max i m u m ra t i ngs t h a t lim i t t h e a n a l o g in p u ts. i n ste a d t h e dig i t a l in pu ts a p plie dt h a t is, cs a nd sclkc a n g o t o 7 v a nd a r e n o t r e s t r i c t e d b y t h e v dd + 0.3 v limi ts as o n t h e a n alog in p u t. th e ma in ad v a n t a g e o f t h e in p u ts n o t b e i n g r e s t ri ct ed t o th e v dd + 0.3 v limi t is tha t p o w e r s u p p l y s e q u en- cin g is s u es a r e a v o i de d . i f cs o r sclk a r e a p plie d befo r e v dd , t h er e is n o r i s k o f la t c h-u p as t h er e w o u l d b e on t h e a n alog in p u ts if a sig n a l g r e a t e r t h a n 0. 3 v w e r e a p plie d p r io r t o v dd . reference a n e x te r n a l s o u r c e i s re qu i r e d t o supp ly t h e re f e re nc e to t h e ad7441/ad74 51. this r e f e r e nce in p u t c a n ra ng e f r o m 100 mv to v dd . th e sp e c if ie d r e fer e n c e is 2.5 v fo r t h e p o w e r su p p ly ra n g e 2.7 v t o 5 . 25 v . the r e f e r e n c e in p u t ch os en f o r a n a p p l ica t io n sh o u ld n e v e r be gr ea t e r than the p o w e r s u p p l y . e r ror s i n t h e re f e re nc e s o u r c e re su lt i n g a i n e r ror s i n t h e ad7441/ad74 51 tra n sf er f u n c tio n and add t o th e sp ecif ie d f u l l -s cale er r o rs o f th e p a r t . a c a p a ci t o r o f a t leas t 0.1 f sh o u ld be p l ace d o n t h e v ref pi n . su it a b l e re f e re nc e s o u r c e s f o r t h e ad7441/ad74 51 in c l ude the ad780 an d t h e ad r421. f i gur e 27 s h o w s a typ i cal co nn ec tion dia g ra m f o r the v ref pi n . 03153-a - 027 1 ad780 nc 8 2 v in nc 7 3 gnd 6 4 temp 5 opsel trim v out ad7441/ ad7451* v ref 2.5v nc v dd nc v dd nc = no connect 10nf 0.1 f 0.1 f 0.1 f *additional pins omitted for clarity f i g u re 27. t y pic a l v ref c o nnec t ion d i agr a m for v dd = 5 v
ad7441/ad7451 rev. a | page 16 of 24 serial interface figure 2 and figure 3 show detailed timing diagrams for the serial interface of the ad7451 and the ad7441, respectively. the serial clock provides the conversion clock and also controls the transfer of data from the device during conversion. cs initiates the conversion process and frames the data transfer. the falling edge of cs puts the track-and-hold into hold mode and takes the bus out of three-state. the analog input is sampled and the conversion initiated at this point. the conversion requires 16 sclk cycles to complete. once 13 sclk falling edges have occurred, the track-and-hold goes back into track mode on the next sclk rising edge, as shown at point b in figure 2 and figure 3. on the 16th sclk falling edge, the sdata line goes back into three-state. if the rising edge of cs occurs before 16 sclks have elapsed, the conversion is terminated and the sdata line goes back into three-state. the conversion result from th e ad7441/ad7451 is provided on the sdata output as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream of the ad7451 consists of four leading zeros, followed by 12 bits of conversion data, provided msb first. the data stream of the ad7441 consists of 4 leading zeros, followed by the 10 bits of conversion data, followed by 2 trailing zeros, which is also provided msb first. in both cases, the output coding is straight (natural) binary. sixteen serial clock cycles are required to perform a conversion and to access data from the ad7441/ad7451. cs going low provides the first leading zero to be read in by the dsp or the microcontroller. the remaining data is then clocked out on the subsequent sclk falling edges, beginning with the second leading zero. thus the first falling clock edge on the serial clock provides the second leading zero. the final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. once the conversion is complete and the data has been accessed after the 16 clock cycles, it is important to ensure that, before the next conversion is initiated, enough time is left to meet the acquisition and quiet-time specifications (see the timing examples that follow). to achieve 1 msps with an 18 mhz clock, an 18-clock burst performs the conversion and leaves enough time before the next conversion for the acquisition and quiet time. in applications with slower sclks, it could be possible to read in data on each sclk rising edge; that is, the first rising edge of sclk after the cs falling edge would have the leading zero provided and the 15th sclk edge would have db0 provided.
ad7441/ad7451 rev. a | page 17 of 24 timing example 1 ha v i n g f sc l k = 18 mh z and a t h r o ug h p u t ra t e o f 1 ms ps g i ves a cy c l e t i m e o f 1/ th r o u g h p u t = 1/1000000 = 1 s a c y cle co n s is ts o f t 2 + 12.5 (1/ f scl k ) + t ac q = 1 s ther efo r e if t 2 = 10 n s , th en 10 n s + 12.5 (1/18 mh z) + t ac q = 1 s t ac q = 296 s this 296 n s s a tisf ies th e r e q u ir em en t o f 290 n s f o r t ac q . fr o m fi g u r e 2 8 , t ac q co m p r i s e s 2.5 (1/ f sclk ) + t 8 = t qu i e t w h er e t 8 = 35 n s . this al lo ws a val u e o f 122 n s f o r t qu i e t , sa ti s f yi n g t h e mi n i m u m r e q u i r em en t o f 60 n s . timing example 2 ha v i n g f sc l k = 5 mh z and a thr o ug h p u t ra t e of 315 ks ps g i v e s a cy c l e t i m e o f 1/ th r o u g h p u t = 1/315000 = 3.174 s a c y cle co n s is ts o f t 2 + 12.5 (1/ f scl k ) + t ac q = 3.174 s ther efo r e if t 2 is 10 n s , th en 10 n s + 12.5 (1/5 mh z) + t ac q = 3.174 s t ac q = 664 n s this 664 n s s a tisf ies th e r e q u ir em en t o f 290 n s f o r t ac q . fr o m fi g u r e 2 8 , t ac q co m p r i s e s 2.5 (1/ f sclk ) + t 8 = t qu i e t w h er e t 8 = 35 n s . this al lo ws a val u e o f 129 n s f o r t qu ie t , sa ti s f yi n g t h e mi n i m u m r e q u i r em en t o f 60 n s . a s i n t h is exa m ple a nd wi t h o t h e r s l o w er clo c k val u es, t h e sig n al m a y alr e a d y b e a c q u i r ed bef o r e th e co n v er si o n is co m p let e , b u t i t is s t il l n e ces s ar y t o lea v e 60 n s minim u m t qu ie t be t w ee n co n v ersio n s. i n e x a m ple 2, t h e s i g n al sh o u ld b e f u l l y acq u ir e d a t a p p r o x im a t e l y p o in t c in f i gur e 28. 03153-a - 028 t 2 t 8 t 6 t 5 t convert cs sclk 12 3 4 5 1 3 1 4 1 5 1 6 12.5(1/f sclk ) t acquisition 1/throughput t quiet 10ns b c f i gure 28. s e ri al inter f ace ti ming e x a m pl e
ad7441/ad7451 rev. a | page 18 of 24 modes of operation the o p er a t in g m o de o f th e ad7451/ad7441 is s e lec t e d b y co n t r o l l in g t h e log i c s t a t e o f t h e cs si gn al d u ri n g a co n v er si o n . ther e a r e tw o op er a t i n g m o des, n o r m a l m o de and p o w e r - down m o d e . t h e p o in t a t w h ich cs is p u l l e d hig h a f t e r t h e con v ersion has b e en i n i t i a te d de t e r m i n es w h et her t h e p a r t en t e rs p o w e r - do wn m o de. si mi la rly , if a l r e ady in p o w e r - dow n , cs co n t r o ls w h et her t h e de v i ce r e t u r n s t o no r m al o p era t ion o r r e ma in s i n p o w e r - do w n . th es e mo des p r o v ide f l exib le p o w e r ma na g e m e n t o p ti o n s th a t ca n o p ti m i z e t h e p o w e r d i s s i p a t i o n / th r o ugh p u t ra t e ra t i o f o r d i f f er in g a p p l ica t io n r e q u ir em en ts. normal m o de this m o d e is in t e nde d fo r fast e s t t h r o ug h p ut ra t e p e r f o r ma n c e . the us er do es no t ha v e t o w o r r y a b o u t an y p o w e r - u p t i m e s w i t h th e ad7441 /ad7451 r e ma inin g f u l l y p o w e r e d u p al l the time . f i g u re 2 9 show s t h e ge ne r a l d i a g r a m of t h e op e r a t i o n of t h e ad7441/ad74 51 in this m o de . the con v ersio n is ini t ia t e d o n th e fal l in g edge o f cs , a s d e sc ri bed i n th e se rial i n t e rf a c e s e c t i o n . t o e n su re t h a t t h e p a r t re m a i n s f u l l y p o we re d up , cs m u s t r e ma in lo w un til a t le as t 10 sclk fal l ing e d g e s ha ve e l a p s e d a f t e r the fal l in g edge o f cs . if cs is b r o u g h t hig h an y tim e a f ter th e 10th sc l k fal l in g e d g e , b u t be f o r e th e 16th sc l k falli n g ed g e , t h e pa r t r e m a i n s p o w e r e d u p b u t t h e con v ersio n is t e r m ina t e d and s d a t a g o es ba c k in t o th r ee-s t a t e . s i xt een seri al c l oc k c y c l e s a r e r e q u i r ed t o co m p let e t h e con v ersio n and ac ces s t h e co m p le t e con v ersio n re su lt . cs ma y idle hig h un til t h e next co n v ersio n o r ma y idle lo w un til so m e t i m e p r i o r t o th e n e xt co n v e r si o n . o n ce a da ta t r a n sfer is co m p let e t ha t is, w h en s d a t a has ret u r n e d t o t h r e e-st a t eano t h e r con v ersio n can b e in i t ia t e d a f t e r t h e q u ie t ti m e , t qu iet , h a s el a p s e d b y ag ai n b r i n g i ng cs lo w . 03153-a - 029 11 0 cs sclk sd a t a 16 4 leading zeros + conversion result f i g u re 29. no r m a l m o de o p er at io n power-down mode this m o d e is in t e nde d fo r us e in a p pli c a t io n s w h er e slo w er th r o ugh p u t ra t e s a r e r e q u i r ed ; ei th e r t h e a d c i s po w e r e d d o wn b e t w e e n e a c h c o n v e r s i on , or a s e r i e s of c o n v e r s i ons m a y b e p e r f o r m e d a t a hig h t h r o ug h p ut r a te and t h e a d c is t h en p o w e r e d do w n fo r a r e la t i vely lon g d u r a t i o n b e t w e e n t h es e b u rs ts o f con v ersio n s. w h en t h e ad7441/ad74 51 is in p o w e r - do wn m o de, a l l a n a l o g cir c ui t r y is p o w e r e d do w n . f o r t h e ad7441/ad74 51 t o en t e r p o wer - do wn m o de , th e con v ersio n pro c e s s m u st b e i n te r r upte d b y b r i n g i ng cs hig h an y w h e r e a f t e r th e s e con d fal l in g edg e o f scl k an d bef o r e t h e 10th fal l in g e d g e of s c l k , a s s h ow n i n fi g u re 3 0 . on ce cs h a s been b r o u gh t hi gh in th i s w i n d o w o f s c l k s , th e p a r t en ters p o w e r - do w n and t h e co n v ersion t h a t w a s in i t i a te d by t h e f a l l i n g e d g e of cs is t e r m ina t e d and sd a t a go es b a ck i n t o th r ee- s t a t e . t h e tim e f r o m t h e ri si n g e d g e o f cs to sd a t a t h r e e-s t a t e ena b le d is ne v e r g r e a t e r t h a n t8 (s e e t h e t i mi n g s p e c if ic a t io n s ). i f cs i s b r o u gh t h i gh be f o r e th e s e c o n d s c lk fa l l in g e d ge, t h e p a r t r e ma in s in n o r m a l m o de and do es n o t p o w e r do wn. t h is a v o i ds a c cid e n t a l p o w e r - do w n d u e to g l i t ches on t h e cs lin e . t o exi t p o w e r - do wn m o de an d p o w e r u p th e ad7441/ad7451 ag ai n , a d u m m y c o n v e r s i on i s p e r f o r me d. o n t h e f a l l i n g e d g e of cs th e de vice b e g i n s t o p o w e r u p , a nd co n t in ues to p o w e r u p as lo n g as cs is h e ld l o w un til a f t e r t h e fal l in g e d ge o f th e 10th sclk. t h e de vi ce is f u l l y p o w e r e d u p a f ter 1 s e c o nd has ela p s e d a n d , as sh o w n in f i gur e 31, valid da t a r e s u l t s f r o m the n e xt co n v ersio n . 03153-a - 030 1 10 sclk s dat a three-state 2 cs f i gure 30. enter i ng p o w e r - d o wn mod e
ad7441/ad7451 rev. a | page 19 of 24 03153-a - 031 cs sclk sdata 1 10 1 6 1 1 0 1 6 a this part is fully powered up with v in fully acquired part begins to power up invalid data valid data t power-up f i g u re 31. e x it ing p o wer - d o wn m o de if cs is b r o u g h t hig h b e f o r e th e 10 th fal l in g e d g e of sclk, th e ad7441 /ad7451 a g a i n g o es bac k in t o p o w e r - do wn. this a v o i ds acci den t al p o w e r - u p d u e t o g l i t ch es on t h e cs lin e o r a n inad v e r t en t b u rs t o f eig h t s c lk c y cles w h i l e cs is lo w . s o al th o u g h th e de v i ce ma y be gin t o po w e r u p o n th e fallin g ed ge of cs , i t a g a i n p o w e rs do wn on the r i sin g edg e o f cs as lo n g as i t o c c u rs b e f o r e th e 10t h scl k fal l in g edge . power-up ti me the p o w e r - u p t i me o f th e ad7 441/ad7451 is typ i cal l y 1 s, wh i c h m e a n s tha t wi t h a n y f r eq uen c y o f sclk u p t o 18 mh z , o n e d u mm y c y cle is al wa ys s u f f i cien t t o al lo w t h e de vic e t o p o w e r u p . on ce t h e d u mm y c y cle is co m p let e , t h e ad c is f u l l y p o w e r e d u p an d t h e i n p u t sig n a l is acq u ir e d p r op erly . the q u iet ti m e , t qu iet , m u st st i l l b e a l l o we d f r om t h e p o i n t a t w h ich t h e b u s g o es b a ck i n t o t h r e e- s t a t e af t e r t h e d u mm y co n v ersio n t o th e n e xt falli n g ed g e o f cs . w h en r u nni n g a t t h e maxi m u m t h r o ug h p ut ra t e o f 1 ms ps, th e ad7441 /ad7451 p o w e r u p a nd acq u ir e a sig n al wi thin 0.5 ls b in on e d u mm y c y c l e , tha t is, 1 s. w h en p o w e r i n g u p f r o m th e po w e r - d o wn m o de wi th a d u mm y c y c l e , a s i n f i gur e 31, t h e t r ack-and- h o ld , w h ich was i n h o ld m o de w h i l e t h e p a r t was p o w e r e d do w n , r e tur n s to t r ack mo de a f ter t h e f i r s t sclk e d g e t h e p a r t r e cei v es a f ter t h e fal l in g e d g e o f cs . this is s h own as p o in t a in f i gur e 31. al th o u g h a t a n y sclk f r eq uen c y o n e d u mm y c y c l e i s s u f f i ci en t to p o w e r u p t h e de vice and ac quir e v in , i t d o e s not ne c e ss ar i l y m e an t h a t a f u l l d u m m y c y cle o f 16 sclks m u st a l wa y s ela p s e to p o w e r u p t h e de vice and ac quir e v in f u l l y ; 1 s is suf f i cien t to p o w e r u p t h e de vice and ac q u ir e t h e in pu t sig n al . f o r e x a m p l e , wh en a 5 mh z sc l k f r eq uen c y i s a p p l i e d t o t h e ad c, t h e c y c l e time is 3.2 s (tha t is, 1/(5 m h z) 16). i n o n e d u mm y c y c l e , 3.2 s, th e p a r t is p o w e r e d u p an d v in acq u ir e d f u l l y . h o w e v e r a f t e r 1 s wi th a 5 mh z sc lk, onl y f i v e sclk c y c l es e l a p s e . a t this s t a g e , th e ad c is f u l l y p o w e r e d u p an d t h e sig n a l acq u ir e d . s o , in t h is c a s e , t h e cs ca n b e b r o u g h t hig h a f ter t h e 10t h scl k fa l l in g e d ge an d b r o u g h t lo w a g ain a f t e r a t i m e , t qu iet , t o ini t i a te t h e con v ersio n . w h en p o w e r s u p p lies a r e f i rs t a p p l ied t o t h e ad7441/ad7451, t h e ad c can p o w e r u p ei t h er in p o w e r - do w n mo de o r n o r m al m o d e . f o r t h i s r e a s o n , i t i s b e s t t o a l l o w a d u m m y c y c l e t o e l a p s e t o ens u r e tha t t h e p a r t is f u l l y p o w e r e d u p bef o r e a t t e m p t i n g a val i d con v ersio n . l i k e wis e , if t h e us er wa n t s t h e pa r t t o po w e r u p i n po w e r - d o wn m o d e , th en th e d u mm y c y c l e ca n be us e d t o en s u r e the devic e is in p o w e r - do wn m o de b y exec u t in g a c y c l e s u c h as tha t sho w n in f i gur e 3 0 . on ce su p p lies a r e a p p l ie d t o t h e ad7441 /ad7451, th e p o w e r - u p tim e is t h e s a me as tha t w h en p o w e r i n g u p f r o m p o w e r - do wn m o de . i t tak e s a p p r o x ima t e l y 1 s t o po w e r u p full y i n n o r m al m o d e . i t i s not ne c e ss ar y to w a i t 1 s b e fore e x e c ut i n g a d u m m y c y cl e to en s u r e t h e desire d m o de o f o p e r a t io n. i n s t e a d , t h e d u mm y c y cle ca n o c cur d i r e ctl y a f t e r p o w e r is s u p p lied t o the ad c. i f the f i rst va lid con v e r sio n is t h e n p e r f o r m e d dir e c t ly a f ter t h e d u mm y con v ersio n , ca r e m u s t b e t a k e n t o en s u re t h a t ade q ua t e acq u isi t ion t i m e has b e en a l lo w e d . a s m e n t ion e d e a rlier , w h e n p o w e r i n g u p f r o m t h e p o w e r - do w n m o de , th e pa r t r e t u rn s t o tra c k m o de u p o n t h e f i r s t sc l k e d g e a p plie d a f t e r t h e fa l l in g e d ge o f cs . h o w e v e r , w h e n t h e a d c p o w e rs u p ini t ia l l y a f t e r su p p lies a r e a p plie d , t h e t r ack-and- h o l d is a l r e ad y in t r a c k m o de . t h is m e an s (assu mi n g o n e has t h e faci li ty t o m o ni to r t h e a d c su pply c u rr en t) t h a t if t h e ad c p o w e rs u p in t h e desir e d m o d e o f o p er a t io n a d u mm y c y cle is n o t r e q u i r e d t o c h a n g e m o d e . t h u s , a d u m m y c y c l e i s a l s o n o t r e q u ir e d t o pla c e t h e t r ack-and- h o ld i n t o t r ack .
ad7441/ad7451 rev. a | page 20 of 24 power vs. throughput rate by usin g t h e p o w e r - do w n m o de o n t h e de vice w h en n o t con v e r - t i n g , t h e a v era g e p o w e r co n s u m p t ion o f t h e a d c de cr e a s e s a t lo w e r th r o ugh p u t ra t e s. f i gur e 32 s h o w s h o w , as th e th r o ugh p u t ra t e is r e d u ce d , th e de vice r e main s in i t s p o w e r - do wn sta t e lo n g er a nd the a v era g e p o w e r con s um p t io n r e d u ces acco r d in g l y . f o r exa m p l e , if th e ad7441 /ad7451 a r e o p era t ed in co n t in uo u s s a m p ling m o de wi t h a thr o ug h p u t ra t e o f 100 ks ps an d an sclk o f 18 mhz, a nd t h e d e vic e is place d i n t h e p o w e r - do w n m o d e b e twe e n co n v ersio n s, t h e n t h e p o w e r co nsum p t ion d u r i n g n o r m al o p era t ion eq uals 9.25 mw max (f o r v dd = 5 v). i f th e po w e r - u p ti m e i s o n e d u m m y c y c l e (1 s) a n d th e r e ma inin g con versio n t i m e is an o t h e r c y cle (1 s), t h en t h e ad7441/ad74 51 ca n be s a id to dis s i p a t e 9.25 mw f o r 2 s d u r i n g e a c h co n v ersio n c y c l e . (this f i gur e as s u m e s a v e r y s h o r t t i me to e n te r p o we r - dow n mo d e . th i s i n c r e a s e s a s t h e b u rst of clo c ks us e d to e n ter p o w e r do w n m o de is in cr e a s e d.) i f th e thr o ug h p u t ra t e = 100 ks ps, th en t h e c y cle time = 10 s a nd t h e a v era g e p o w e r dis s i p a t e d d u r i n g e a ch c y cle is (2/10) 9.25 mw = 1.85 mw f o r th e sa m e sce n a r i o , i f v dd = 3 v , t h e p o w e r d i ssi p a t ion d u r i ng n o r m al o p er a t io n is 4 mw max. the ad7441/ad7451 can n o w be s a id t o dis s i p a t e 4 mw f o r 2 s 1 d u r i n g each con v ersio n c y c l e . the a v er a g e p o w e r dis s i p a t e d d u r i n g e a ch c y cle wi t h a thr o ug h p u t ra t e o f 100 ks ps is th er ef o r e (2/10) 4 mw = 0.8 mw this is h o w t h e p o w e r n u m b ers in f i gur e 32 a r e ca lc u l a t e d . 03051-a - 044 throughput (ksps) 100 0 350 p o we r (mw) 0.01 50 100 150 200 250 300 0.1 1 10 v dd = 5v v dd = 3v f i gure 32. p o wer v s . thro ughput r a te f o r p o wer - d o w n m o de 1 this figure assumes a very short time to enter power- do wn mode. this incre a s e s as the burs t of cl o c ks us ed to e nte r po we r do wn mo d e is i n crea sed. f o r o p tim u m p o w e r p e r f o r ma n c e in thr o ugh p u t ra t e s abo v e 320 ks ps, i t is reco mm en de d t h a t t h e s e r i al c l o c k f r eq uen c y be r e d u ced . microproc e ssor and dsp inter f acing the s e r i al in ter f ace o n t h e ad7 441/ad7451 al l o ws th e p a r t t o b e co n n e c te d di r e c t ly to a r a n g e o f dif f er en t mic r o p r o cess o r s. this s e c t ion ex p l a i n s h o w t o in t e r f ace the ad7 441/ad7451 wi t h s o m e o f t h e m o r e com m on micr o c on t r ol ler and ds p s e r i a l in ter f ace p r oto c ols. ad7441/ad7451 to adsp-2 1xx the a d s p -21xx fa mil y o f ds p s a r e in t e r f ace d dir e c t l y t o t h e ad7441/ad74 51 wi t h o u t an y g l ue log i c r e q u ir ed . th e s p o r t c o n t ro l re g i ste r shou l d b e s e t up a s f o l l ow s : t f sw = rfsw = 1 al t e r n a t e f r a m in g invrfs = inv t fs = 1 a c ti v e lo w f r a m e sig n al d t yp e = 00 rig h t j u s t if y da t a s l en = 1111 16-b i t da ta-w o r ds i s c l k = 1 i n t e rn al se rial c l oc k t f sr = r f sr = 1 fr ame e v e r y word irfs = 0 itfs = 1 t o im p l em en t p o w e r - do wn m o de , s l en s h o u l d b e s e t t o 1001 to issu e an 8 - bi t s c l k b u rst. the co nn ec tion dia g ra m is sh own in f i gur e 33. the ads p -21xx h a s th e t f s a n d r f s o f th e s p o r t ti e d t o g e t h e r , w i t h t f s set as a n o u t p ut and rfs s e t as a n i n p u t. t h e dsp o p era t es in a l ter n a t e f r a m ing m o de, an d t h e s p or t con t r o l r e g i ster is s e t up a s d e s c r i b e d. t h e f r am e s y nc h r on i z a t i o n s i g n a l ge ne r a te d o n th e t f s i s tied t o cs , and, a s w i t h a l l s i g n a l pr o c e s s i ng a p pl i - ca t i on s, e q uidi st a n t s a m p li n g is n e ce ss a r y . h o w e v e r , in t h is exa m ple , t h e t i m e r i n t e r r u p t is us e d t o co n t r o l t h e s a m p lin g ra te of t h e a d c , a n d, u n d e r c e r t ai n c o nd i t i o ns , e q u i d i st a n t s a m p l i n g ca nn o t be achie v ed . 03153-a - 033 ad7441/ ad7451* adsp-21xx* sclk dr rfs tfs sclk sdata cs *additional pins removed for clarity f i g u re 33. inte r f a c i n g to t h e a d s p - 21x x
ad7441/ad7451 rev. a | page 21 of 24 the t i m e r r e g i s t ers, fo r e x a m ple , a r e lo ade d wi t h a val u e t h a t p r o v ides a n in te r r u p t a t t h e r e quir e d s a m p le in ter v a l . w h e n a n in t e r r u p t is r e ce i v e d , a v a l u e is t r a n smi t t e d wi t h tfs/dt (ad c co n t r o l w o r d ). the tfs is us e d t o co n t r o l t h e rfs a nd t h er efo r e th e r e a d i n g o f da ta . th e f r eq ue n c y o f th e se ri al cloc k i s se t in t h e sc lkd i v reg i s t er . w h en t h e in s t r u c t io n t o t r a n smi t w i t h t f s i s gi v e n , tha t i s , ax 0 = t x 0, th e s t a t e o f th e sc l k i s c h e c k e d . t h e d s p w a i t s u n ti l th e s c l k h a s g o n e h i gh , l o w , a n d h i gh be f o r e s t a r ti n g tra n sm is si o n . i f th e t i m e r a n d sc lk v a l u e s a r e c h os en s u c h tha t t h e ins t r u c t io n t o tra n smi t o c c u rs o n o r n e a r t h e r i sin g e d g e o f sclk, t h en t h e da ta ma y be tra n s m i t t e d or it m a y w a it u n t i l t h e n e x t c l o c k e d g e . f o r exa m p l e , th e ads p -2111 has a mas t er c l o c k f r eq uen c y o f 16 mh z. i f t h e sclkd i v r e g i st er is lo ade d wi t h t h e val u e 3, a n scl k o f 2 mh z is ob tained , a nd eig h t mas t er c l o c k p e r i o d s e l a p s e fo r e v er y o n e s c lk p e r i o d . i f t h e t i m e r r e g i s t ers a r e lo aded wi th t h e val u e 803, 100.5 sclks o c c u r b e tw een in t e r - r u p t s and su bs e q u e n t ly b e twe e n t r ans m i t inst r u c t ions . this si t u a t ion r e su l t s in n o n e q u i d ist a n t s a m p li n g b e ca us e t h e t r a n smi t in st r u c t io n is o c c u r r i n g o n a n s c lk e d ge . i f t h e n u m b er o f sclks b e twe e n in te r r u p ts is a w h ol e in teger f i gur e o f n, eq uidis t a n t s a m p lin g is im p l em en t e d b y the ds p . ad7441/ad7451 to tms320c5x/c54x the s e r i al in ter f ace o n t h e t m s 320c5x/c54x us es a co n t in uo u s s e r i al c l o c k and f r a m e sy n c hr o n iza t io n sig n als t o syn c hr o n ize t h e da t a t r an sfer o p era t io n s w i t h p e r i ph eral de vices s u ch as th e ad7441 /ad7451. the cs in pu t a l lo ws e a sy in t e r f acin g betw een t h e tms320c5x/c54 x a n d t h e ad74 41/ad7451 w i th o u t a n y gl u e l o gi c r e q u i r ed . t h e se ri al po r t o f th e t m s320c5x/c54x is s e t u p t o o p era t e in b u rs t m o de wi t h i n t e rn al clkx (t x seri al c l ock) a n d fsx (t x f r a m e sy n c ). t h e ser i al p o r t co n t r o l r e gis t er (s pc) m u s t ha ve the f o ll o w in g set u p: fo = 0, fs m = 1, m c m = 1 a n d t x m = 1. th e f o r m a t b i t, fo , ca n b e s e t t o 1 to s e t t h e w o r d len g t h t o 8 b i ts i n o r der t o im p l em en t t h e p o w e r - do wn mo de o n t h e ad7 441/ad7451. the co nn ec tion dia g ra m is sh own in f i gur e 34. n o t e tha t f o r sig n a l p r o c essing a p plic a t ion s , t h e f r am e sy n c hr o n iz a t ion sig n a l f r o m th e t m s3 20c5x/c54x m u s t p r o v ide eq uidis t an t s a m p ling. ad7441/ ad7451* tms320c5x/ c54x* clkx dr fsx fsr sclk sdata cs clkr 03153-a - 034 *additional pins removed for clarity f i g u re 34. inte r f a c i n g to t h e tm s 3 2 0 c 5 x / c5 4x ad7441/ad7451 to dsp56xxx the co nn ec tion dia g ra m in f i g u r e 35 s h o w s h o w the ad7441/ ad7451 can be co nnec t e d t o t h e ss i (sy n c h r o no us s e r i al in t e r f ace) o f th e ds p56xxx fa m i l y o f ds p s f r o m m o t o r o la . th e ss i is o p era t ed in sy n c hr on o u s m o de (s yn b i t in crb = 1) wi t h i n te r n a l ly ge ne r a te d 1 - b i t cl o c k p e r i o d f r ame s y nc for b o t h tx a nd rx (bi t f s l 1 = 1 a n d bi t f s l0 = 0 in crb). s e t t h e w o r d len g th t o 16 b y s e t t in g b i ts wl 1 = 1 a n d wl0 = 0 in cra. t o im p l em en t t h e p o w e r - do wn mo de o n t h e ad7 441/ad7451, t h e w o rd len g t h ca n b e ch a n ge d t o eig h t b i ts b y s e t t i n g b i ts wl1 = 0 an d wl0 = 0 in cra. n o t e tha t f o r sig n al p r o c es sin g a p plic a t ion s , t h e f r a m e sy n c hr oniz a t ion sig n a l f r o m t h e ds p56xxx m u s t p r o v id e eq uid i sta n t s a m p lin g . ad7441/ ad7451* 03153-a - 035 dsp56xxx* sclk srd sr2 sclk sdata cs *additional pins removed for clarity f i g u re 35. inte r f a c i n g to t h e ds p 56x x x
ad7441/ad7451 rev. a | page 22 of 24 grounding and layout hints the printed circuit board that houses the ad7441/ad7451 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separ- ated. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should be joined in only one place, a star ground point established as close to the gnd pin on the ad7441/ad7451 as possible. avoid running digital lines under the device as this couples noise onto the die. the analog ground plane should be allowed to run under the ad7441/ad7451 to avoid noise coupling. the power supply lines to the ad7441/ad7451 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital grounds to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough on the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device. evaluating performance the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the evaluation board controller. the evaluation board controller can be used in conjunction with the ad7441 and the ad7451 evaluation boards, as well as with many other analog devices evaluation boards ending with the cb designator, to demonstrate and evaluate the ac and dc performance of the ad7441 and the ad7451. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad7441/ad7451. see the ad7441/ad7451 application note that accompanies the evaluation kit for more information.
ad7441/ad7451 rev. a | page 23 of 24 outline dimensions 13 5 6 2 8 4 7 2.90 bsc pin 1 1.60 bsc 1.95 bsc 0.65 bsc 0.38 0.22 0.15 max 1.30 1.15 0.90 seating plane 1.45 max 0.22 0.08 0.60 0.45 0.30 8 4 0 2.80 bsc compliant to jedec standards mo-178ba figure 36. 8-lead small outline transistor package [sot-23] (rt-8) dimensions shown in millimeters 0.80 0.60 0.40 8 0 4 85 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc coplanarity 0.10 0.23 0.08 compliant to jedec standards mo-187aa figure 37. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters
ad7441/ad7451 rev. a | page 24 of 24 ordering guide model temperature r a nge linearity error (lsb) 1 package descri ption package option branding ad7451art- r 2 ?40c to +85c 1.5 8-lead sot-23 rt-8 c06 ad7451art- r ee l7 ?40c to +85c 1.5 8-lead sot-23 rt-8 c06 ad7451arm ?40c to +85c 1.5 8-lead msop rm-8 c06 ad7451arm- r e el7 ?40c to +85c 1.5 8-lead msop rm-8 c06 ad7451brt-r2 ?40c to +85c 1 8-lead sot-23 rt-8 c05 ad7451brt-re e l 7 ?40c to +85c 1 8-lead sot-23 rt-8 c05 ad7451brm ?40c to +85c 1 8-lead msop rm-8 c05 ad7451brm-re el7 ?40c to +85c 1 8-lead msop rm-8 c05 ad7441brt-r2 ?40c to +85c 0.5 8-lead sot-23 rt-8 c0f ad7441brt-re e l 7 ?40c to +85c 0.5 8-lead sot-23 rt-8 c0f ad7441brm ?40c to +85c 0.5 8-lead msop rm-8 c0f ad7441brm-re el7 ?40c to +85c 0.5 8-lead msop rm-8 c0f eval-ad7451c b 2 evaluation bo ar d eval-ad7441c b 2 evaluation bo ar d eval-control brd2 3 controll er boar d 1 linearity error her e re fer s to integral nonlinearity error. 2 th i s ca n be use d a s a st a n da lon e eva l ua t i on boa r d or i n c o n j u n c t i on with t h e eval uat i on board con t r oll e r for evalu a t i on /demon st ration purpose s . 3 th e eva l ua t i on boa r d con t r o lle r i s a c o m p let e un i t a llowi n g a p c t o con t r ol a n d com m u n i ca t e wi t h a ll an a l og d e vi c e s eva l ua t i on boa r ds en di n g i n t h e cb de si gn a t ors. to or der a comp let e eva l uation kit, you must order the adc evaluation boar d (eval-a d7451cb or eval-ad7441cb) , the eval-control brd2, and a 12 v ac transformer. see the ad7451/ad7441 applicat ion note th at accompanies the eval uation kit for more information. ?2004 anal og de v i ces, inc. all ri ghts reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c03153-0-2/04(a)

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